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VGA text controller v1.0 - 05/05/2001

"VGA text controller for Xess XS40-v1.4"

Readme file


Distribution binaries : (demo HEX and BIT files only) (demo files, with source schematics and Verilog files)


Project Description

"VGA-text controller" is a digital logic circuit to demonstrate a video display application in small FPGAs (Xilinx XC4000XL.) This package contains design and demonstration files for an Xess XS40 VGA-text controller.

A text-controller is an alphanumeric (character-code) based display. Unlike a graphics-display which is pixel-addressable, the text-display is restricted to a fixed set of character blocks, much like an old-fashioned typewriter is restricted to a limited set of printed characters. The framebuffer memory stores both the text-screen and font-bitmap. The text-screen is the character-coded 2D-grid of alphanumeric characters. The font-bitmap defines the appearance of each alphanumeric-character, sort of like a digital graphical alphabet.

Currently, there is no support for graphics modes ('all pixels addressable')


The contents of this pacakge are subject to the GNU Public License Agreement; you may not use this file except in compliance with this Agreement. See the LICENSE file.


Controller Specifications


Display-resolution = 640x480 60Hz (31.5KHz VGA) : 25.00MHz pixclk

Text screen resolution = 80x30 alphanumeric characters, 1-byte per char

Color palette : foreground=white, background=black (monochrome only)


Framebuffer memory type = 8-bit wide asynchronous SRAM

bandwidth usage = roughly 2 accesses per 8 clocks (25%)


Font character resolution = 8 x YY character cell (YY=programable, 1..31)

Font depth = 256 addressable bitmaps


Single master clock input = 25.00MHz (for pixclk, and all controller logic)


Design description language : synthesizable (RTL) Verilog HDL


Built and tested on Xess XS40-010XL+ v1.4, and compatible with any XS40 v1.4 board


Running the Demo


You'll need the following equipment to see the text-demo :

Xess XS40 v1.4 board (must be v1.4 or later!)

Xess's "XSTOOLs" package installed on your Windows PC, to download the demo files into the XS40

VGA monitor (and optionally a PC keyboard with PS/2 connector)


First, set the XS40's oscillator frequency to 25MHz ('divider=4'.) Use Xess's program XSSETCLK to do this.

Then run XSLOAD. Using Windows Explorer, open up the folder/directory that contains the BIT-files (from this package.)

You are ready to download the demo to your FPGA_board! You must choose the correct fileset bassed on your XS40 hardware :


1) Xess XS40-005xl v1.4 (XC4005XL) - e4005p25.bit + ega_gf2mx.hex

< or >

v4005p25.bit + vga_gf2mx.hex


2) Xess XS40-010xl v1.4 (XC4010XL) - e4010p25.bit + ega_gf2mx.hex

< or >

v4010p25.bit + vga_gf2mx.hex


There are two demos for each of the two supported devices (4005XL and 4010XL.) The 'EGA' demo uses a fontmap of 8x14, displayed at a VGA resolution of 640x480. The 'VGA' demo uses

Drag the appropriate BIT file (4005 or 4010) and HEX file onto XSLOAD's application window. Ignore the error dialog, if one pops up. After you have dragged the HEX and BIT files to the XSLOAD's application window, you should see the names of both files in XSLOAD's application window.

Finally, highlight both the HEX and BIT file, then click 'RELOAD.' The PC will now download these files to the XS40.


To look at the demo, connect a VGA monitor to the XS40's VGA connector. You can also connect a PS/2 keyboard to the XS40. A scancode-reader will capture and print the scancodes to a small section of the demonstration text screen. Note that the scancodes are byte-encodings for the keyboard's individual keys, and bear NO resemblance to the letter-printed on that key.

Alternatively, you can connect a PS/2 mouse to the Xess's PS/2 port. As you move the mouse, the mouse's motion tracking will send movement scancodes to the XS40.


Design Hierarchy


If you're interested in the source files for the design, here's an overview of the design hierarchy. The primary logic is lcoated in CRTTIME2.V. The rest of the source files are more or less support logic.


Top-level files :


These three top-level files are schematics showing the connectivity (signal interfacing) between the TEXT-controller, PS/2 port-scanner, and the SRAM framebuffer.


Top_clk.sch - provides clock input (from IOpad), clock driver to rest of FPGA chip

Output : sysclk25, rstn (global active-low reset line)

Top_kbd.sch - PS/2 keyboard input module, captures byte-scancodes from PS/2 device, writes scancode into XS40 SRAM.

Output : o_byte[7:0], o_byte_rdy, o_byte_err


Toplevel.sch - VGA text controller, SRAM-address mux

The text-controller generates a VGA-like text display.

Output : VGA R,G,B signal lines, VGA vsync/hsync control lines


Xs40_vga.ucf - Xilinx constraint files (IOPAD pin assignment/naming, timing constraints)


Support files :


These Verilog source files are for the KBSCAN, KBWRITE, and CRTTIME2 schematic symbols. All are synthesizable with Xilinx Foundation Synopsys FPGA-Express compiler.


Crttime2.v - RTL source code for the VGA text controller

\--- > mult8x5u.v - RTL source code for an 8x5 unsigned multiplier (address calculation)

kbscan.v - RTL source code for simple PS/2 port reader

kbwrite.v - RTL source code for simple circuit to transfer kbscan.v's output into XS40's SRAM


As you can see, the design hierarchy is very 'flat'! The entire project was created and compiled in Xilinx Student Edition 2.1I using a 'schematic flow.' The entire design is a mixture of synthesized Verilog macros and Xilinx schematic sheets. The Verilog macros implement the core logic functionality of the entire circuit. The schematics provide connectivity between the major logic blocks and the XS40 IO-pads.


If you want to rebuild the project yourself, you'll need to use Logiblox to create a 16-bit wide, 2:1 multiplexor. The 16-bit multiplexor (used in toplevel.sch) choses the output SRAM-address.



Demonstration files :


Included in this distribution are precompiled BIT files and sample font-bitmaps (HEX files.) All you need is an Xess XS40 v1.4 board and an installation of Xess's XSTOOLs software. XSTOOLs enables you to download these demo files to the XS40-FPGA device.


E4005p25.bit - bitstream file for XS40-005XL v1.4 FPGA-board, EGA-text (8x14 char)

V4005p25.bit - bitstream file for XS40-005XL v1.4 FPGA-board, VGA-text (8x16 char)

E4010p25.bit - bitstream file for XS40-010XL v1.4 FPGA-board, EGA-text (8x14 char)

V4010p25.bit - bitstream file for XS40-010XL v1.4 FPGA-board, VGA-text (8x16 char)


ega_gf2mx - EGA (8x14) 256-character font captured from a Geforce2/MX

vga_gf2mx - VGA (8x16) 256-character font captured from a Geforce2/MX


Vgafontc.exe - DOS program to capture font-bitmaps from your PC's VGA BIOS

Output : vgafontc.out - binary bitmap dump of the font

vgafontc.hex - the same info, but this dump is XSLOAD-compatible


vgafontc.c - C-source file for vgafontc.exe (Borland Turbo C++ 3.0 DOS)


Technical information


The verilog source files contain code comments to help others understand the module's underlying signal generation theory as well as actual implementation. But interested uesrs should have a basic background in raster display-controller concepts. Richard Ferraro's "Programmer's guide to the EGAand VGA cards" is an excellent book (but unfortunately, it's out of print.)


Bugs and Defects


The PS/2 capture circuit is shaky. Due to a simplified memory controller, the circuit ocassionally writes to the wrong address, causing random character changes on the text display. Also, while the PS/2 capture circuit can detect parity errors, it takes no action after an error event. If the keyboard/mouse is unplugged while the XS40 is active, the capture-circuit 'goes out of sync' with the device's serial transmitter. The XS40 must be powered off/on, then reprogrammed to re-establish a good link.


The text display is visibly unstable, as if suffering from electrical interference. This happens on the author's development board ,too. My CTX PR710 has no problem synchronizing to the VGA signal, but the Viewsonic P810 that I use at work seems to wander in and out of signal lock. I alleviated thisby doubling pixclk from 25Mhz to50MHz. Using the same CRTC parameters, the horizontal scan frequency doubles from 31.5KHz to 63KHz, which is well within the P810's input frequency range. Note, the demo BIT files will ONLY RUN AT 25MHz! (To change to 50MHz, you must modify and recompile the project.)


The CRTC parameters stored in the crttime2.v file do not fully match VGA-specification. A modern VGA multisync monitor should have no trouble with the imprecise timings, but early VGA monitors may not work! CAUTION!


The source design targets the XS40-v1.4 boards only. If you want to use the text-controller with different FPGA-boards, you'll need to modify the source code and recompile the project. Earlier revisions of the XS40 cannot supply the 25MHz pixclk.

Useful Links - makers of the Xess XS40 board, and many other FPGA boards - Gray Research homepage, XSOC 'system on a chip' for XS40 - VGADOC homepage, a collection of register-level programming information for VGAs


License Agreement


This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version.

This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.

You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., - 05/05/2001